This invention relates to semiconductor devices, and more particularly to a series pair of N-channel silicon gate transistors and a process for making them.
In MOS integrated circuits such as sense amplifiers for dynamic memory arrays, or in various logic gates, pairs of transistors are connected with their source-to-drain paths in series. Usually a shared source/drain region between the two is a diffused N+ region, which occupies unnecessary space on the chip and introduces unwanted overlap capacitance and node capacitance, slowing the operation of the circuit.
A double level polysilicon process is widely used to make one-transistor memory cells, as described in U.S. patent applications Ser. No. 648,594, filed Jan. 12, 1976, and No. 722,841, filed Sept. 13, 1976, now U.S. Pat. No. 4,240,092 assigned to Texas Instruments. In this process, a capacitor is formed by the first level poly, and the transistor gate is formed by the second level which partly overlaps the first. Heretofore, the advantages of this structure have not been utilized in a series transistor structure.
It is the principal object of this invention to provide a semiconductor device in the form of a series transistor pair of small size and with reduced overlap capacitance and node capacitance. Another object is to provide a small-area series transistor pair which is made by a process compatible with standard N-channel silicon gate manufacturing techniques.